Random defects (e.g. particles) can cause electrically measurable faults (killer defects), which are dependent on the chip layout as well as the layer and location of the defects. Also, certain layout geometries can cause systematic faults dependent on specific combinations of layout and manufacturing process steps. Random as well as systematic faults are responsible for manufacturing related malfunction of chips. So, investigating random and systematic faults is important for yield enhancement and to control quality of process steps and product chips, as discussed in Staper, C. H., Rosner, R. J., “Integrated Circuit Yield Management and Yield Analysis: Development and Implementation,” IEEE Transactions on Semiconductor Manufacturing, pp. 95-102, Vol. 8, No. 2, 1995, which is incorporated by reference herein. Test structures are used to detect faults, to identify and localize defects, as well as to characterize systematic manufacturability of layout geometries.
Many test structures like via or contact chains, snake and comb lines etc. have been described to detect defects, e.g. in Ipri, A. C., Sarace, J. C., “Integrated Circuit Process and Design Rule Evaluation Techniques,” RCA Review, pp. 323-350, Volume 38, Number 3, September 1977, and Buehler, M. G., “Microelectronic Test Chips for VLSI Electronics,” VLSI Electronics Microstructure Science, pp. 529-576, Vol 9, Chapter 9, Academic Press, 1983, both of which are incorporated by reference herein. Two parallel via chains as described in Doong, K., Cheng, J., Hsu, C., “Design and Simulation of Addressable Fault Site Test Structure for IC Process Control Monitor,” International Symposium on Semiconductor Manufacturing, 1999, which is incorporated herein by reference. Multiple interwoven via chains which allow for the detection of open and short circuits are described in Hess, C., Weiland, L. H., “Influence of Short Circuits on Data of Contact & Via Open Circuits Determined by a Novel Weave Test Structure,” IEEE Transactions on Semiconductor Manufacturing, pp. 27-34, Vol. 9, No. 1, 1996, which is incorporated herein by reference. To characterize the density and size distribution of random defects a NEST test structure is described at Hess, C., Stashower, D., Stine, B. E., Weiland, L. H., Verma, G., Miyamoto, K., Inoue, K., “Fast Extraction of Defect Size Distribution Using a Single Layer Short Flow NEST Structure”, IEEE Transactions on Semiconductor Manufacturing, pp. 330-337, Vol. 14, No. 4, 2001, which is incorporated herein by reference.
However, all those test structures are connected to individual pads for testing. Far more than 1000 differently designed test structures per layer may be required to achieve yield and performance improvements as described in detail in U.S. Pat. No. 6,449,749, entitled: System and Method for Product Yield Prediction and in U.S. Provisional Application No. 60/437,922, entitled YIELD IMPROVEMENT, filed on Jan. 2, 2003, both of which are incorporated by reference herein. It is difficult or impossible to place all those test structures on a single test chip if they are all connected to individual pads for testing, since there is not enough area to place all those pads. Methods of pad sharing are used to address and access individual test structures by significantly reducing the number of pads required for testing.
To do so, single vias have been placed in a passive array where each via is connected to a unique set of two lines as described in detail at Walton, A. J., Ward, D., Robertson, J. M., Holwill R. J., “A Novel Approach for an Electrical Vernier to Measure Mask Misalignment”, 19th European Solid State Device Research Conference ESSDERC'89, Springer Verlag, 1989, which is incorporated herein by reference. But Walton et al. required that all structures (in this case a single via) are the same within such an array. If one were to place differently designed test structures within such an array, the test procedure would fail. The array also does not allow any fast digital testing.
A similar array is described by Hess, C., Stine, B. E., Weiland, L. H., Mitchell, T., Karnett, M., Gardner, K., “Passive Multiplexer Test Structure For Fast and Accurate Contact and Via Fail Rate Evaluation”, Proc. International Conference on Microelectronic Test Structures (ICMTS), Cork (Ireland), 2002, which is incorporated herein by reference. It places long via chains in an array to break down the huge chain resistance for testing. Fast digital testing is possible, but again all test structures within the array had to be identical. This technique is of no help, if differently designed test structures have to be placed on a test chip.
The passive array as mentioned above can be expanded by a transistor, which is placed in serial connection to each test structure as described at Walton, A. J., Gammie, W., Marrow, D., Stevenson, J. T. M., Holwill, R. J., “A novel Approach for Reducing the Area Occupied by Contact Pads on Process Control Chips”, International Conference on Microelectronic Test Structures, San Diego, (USA), 1990, which is incorporated herein by reference.
None of the methods mentioned above, allow stacking of structures in multiple layers on top of each other to efficiently make use of 10 or more routing layers that are commonly used in semiconductor manufacturing. Also, all these arrays are only able to investigate open circuit faults and are of no use if also short circuits have to be investigated. A method to permute pairs of lines has been described at Hess, C., Weiland, L. H., Bornefeld, R., “Customized Checkerboard Test Structures to Localize Interconnection Point Defects”, Proc. VLSI Multilevel Interconnection Conference (VMIC), pp. 163-168, Santa Clara (USA), 1997 and Hess, C., Weiland, L. H., “Defect Parameter Extraction in Backend Process Steps using a Multilayer Checkerboard Test Structure”, Proc. International Conference on Microelectronic Test Structures (ICMTS), pp. 51-56, Nara (Japan), 1995, both of which are incorporated by reference herein. Using those methods it is possible to place many test structures within a reduced number of pads to investigate short circuits. No active devices are needed, and it is possible to place multiple structures on top of each other over an unlimited number of routing layers. Unfortunately, these methods are limited to short circuits only and they have problems in disentangling multiple faults, if they occur in more than one test structures as it has been reported at Hess, C., Weiland, L. H., “Strategy to Disentangle Multiple Faults to Identify Random Defects within Test Structures”, Proc. International Conference on Microelectronic Test Structures (ICMTS), pp. 141-146, Kanazawa (Japan), 1998, which is incorporated herein by reference.
A test structure has been introduced to investigate defect densities as well as defect size distributions in multiple layers as described in detail at Hess, C., Weiland, L. H., “Harp Test Structure to Electrically Determine Size Distributions of Killer Defects”, IEEE Transactions on Semiconductor Manufacturing, pp. 194-203, Vol. 11, No. 2, 1998, which is incorporated herein by reference. It uses the same method of permuting pairs of lines. Even though disentangling multiple faults is rarely a concern in this case, the method still only works for short circuits.
The method of permuting lines has been combined with a diode array as being described at Hess, C., Weiland, L. H., “Drop in Process Control Checkerboard Test Structure for Efficient Online Process Characterization and Defect Problem Debugging”, Proc. International Conference on Microelectronic Test Structures (ICMTS), pp. 152-159, San Diego (USA), 1994, which is incorporated herein by reference. A more advanced method has been based on transistors as it is described at Hess, C., Weiland, L. H., Lau, G., Simoneit, P., “Control of Application Specific Interconnection on Gate Arrays Using an Active Checkerboard Test Structure”, Proc. International Conference on Microelectronic Test Structures (ICMTS), pp. 55-60, Trento (Italy), 1996, which is incorporated herein by reference. Even though it is now possible to evaluate open and short circuits in test structures that can be placed in multiple layers on top of each other, it is still a problem to disentangle multiple short circuit faults. This is even more of a problem if differently designed test structures are used, since some of them can fail all the time, if design rule margins are explored.
A variety of test structures are placed within shared pads using some of the methods mentioned so far can be found at Doong, K, Hsieh, S., Lin, S., Shen, B. Cheng, J., Hess, C., Weiland, L., Hsu, C., “Addressable Failure Site Test Structures (AFS-TS) for CMOS Processes: Design Guidelines, Fault Simulation, and Implementation”, IEEE Transactions on Semiconductor Manufacturing, pp. 338-355, Vol. 14, No. 4, 2001, which is incorporated herein by reference. Unfortunately, there is no stacking of test structures, which is a very inefficient test chip area usage if 10 or more routing layers are available.
Multiplexer circuitry is being used to address test structures as described at Ward, D., Walton, A. J., Gammie, W. G., Holwill, R. J., “The Use of a Digital Multiplexer to Reduce Process Control Chip Pad Count”, International Conference on Microelectronic Test Structures 1992, San Diego (USA), 1992, which is incorporated herein by reference. However, such test structures require that the multiplexing circuitry is working without failures. Thus, a stable working manufacturing process is required, which disqualifies this method for the early development stages of a new semiconductor manufacturing process. This technique does not allow one to apply any analog resistance and leakage measurements through the multiplexing circuitry, which is required to characterize so-called soft faults.
All those methods described above have in common that they place existing test structures like parallel lines, via chains, snake and combs, etc. in a way that reduces the number of pads for testing. But, there are significant limitations in how to use those methods, which prohibits their universal usage.
Beside using test structures, also SRAM or ROM based test chips have been developed for defect detection and process characterization as been described for instance in Khare, J., Maly, W., Griep, S., Schmitt-Landsiedel, D., “SRAM-based Extraction of Defect Characteristics”, International Conference on Microelectronic Test Structures, San Diego, USA, 1999, which is incorporated herein by reference. Such test structures use decoders and similar complicated circuitry to address memory cells. Only if those logic blocks work without faults is it possible to detect faults in the memory cells. Beside that, it is difficult and sometimes impossible to assign a fault of a memory cell to a layout object in a specific layer, which is essential for process characterization and successful yield and performance improvement. Also, memory cells have a very uniform layout and neighborhood as well as a specific density of layout objects per layer, which does not necessarily reflect the geometries of random logic layout designs. Finally, this method does not allow one to apply analog resistance and leakage measurements to one specific memory cell.
More efficient methods to place test structures within a test chip are desired.